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TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Table 5-14. Timing Requirements for EMIF Asynchronous Memory (1) (2) (see Figure 5-18 , Figure 5-20 , and
Figure 5-21 )
CV DD = 1.05 V
NO.
DV DDEMIF = 3.3/2.75/2.5/1.8 V
UNIT
READS and WRITES
MIN
NOM
MAX
2
t w(EM_WAIT)
Pulse duration, EM_WAITx assertion and deassertion
2E
ns
READS
12
13
t su(EMDV-EMOEH)
t h(EMOEH-EMDIV)
Setup time, EM_D[15:0] valid before EM_OE high
Hold time, EM_D[15:0] valid after EM_OE high
14.5
0
ns
ns
14
t su (EMOEL-EMWAIT)
Setup time, EM_WAITx asserted before end of Strobe Phase
(3)
4E + 13
ns
WRITES
28
t su (EMWEL-EMWAIT) Setup time, EM_WAITx asserted before end of Strobe Phase (3)
4E + 13
ns
(1)
(2)
(3)
E = SYSCLK period in ns. For example, when SYSCLK is set to 100/120 MHz, E = 10/8.33 ns, respectively.
Timing parameters are obtained with 10pF loading on the EMIF pins.
Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended
wait states. Figure 5-20 and Figure 5-21 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Copyright ? 2010–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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